Precise Improvements to Power Control for Advanced Silicon Devices
As process geometries have reduced the density increases have enabled increasingly complex microprocessors, DSPs and FPGAs to be implemented. But the deep submicron geometries in use have narrowed the supply-rail tolerances that these devices require to operate.
As process geometries have reduced the density increases have enabled increasingly complex microprocessors, DSPs and FPGAs to be implemented. But the deep submicron geometries in use have narrowed the supply-rail tolerances that these devices require to operate.
In order to achieve high speed and low power dissipation, high-integration microprocessor, DSP and FPGA chips require voltage levels of 1 to 3.3V DC with a tolerance of as little as ±30mV. At the same time, these complex ICs require dynamic changes in input current for short periods of time. These types of requirements place severe demands upon the power system. Most power system handle fast dynamic current profiles through the use of decoupling capacitors located close to the electronic circuits. The power supply handles low frequency and longer duration dynamic demands.
Fig. 1 – Principals of dynamic response
A combination of the control loop used by the power supply, the distribution impedance and the decoupling capacitors decides how the dynamic current is shared between the decoupling capacitance and the power supply.
One way in which the design can be supported is to make intensive use of decoupling capacitors. Many FPGA-based boards now contain numerous capacitors, all designed to smooth out power transients. If fewer output decoupling capacitors can be used to insure a given voltage tolerance the result will be a lower bill-of-materials cost. It will also have a huge impact and pay-off in terms of reduced time-to-market and increased system packaging density.
High-performance digital control allows this system to be further tuned for the target load and support dynamic current profiles while satisfying the requirement for low tolerance in voltage levels.
Digital control is not a magic wand that can twist the physical laws, but it makes it possible to improve and optimise the dynamic response performance because the digital protocol does not have to take into account any tolerance problems, which are the case for the capacitive and resistive networks used in analogue control loops. However, design of these control loops can be complex and time-consuming if performed manually.
To aid the design of power-supply control loops, Ericsson now offers a useful software tool that designs, simulates, analyses and configures the point-of-load (POL) regulator. Using the tool it is possible to build effective control-loop settings within minutes. The software includes simple tools for the robust design of control loops, together with more advanced design and analysis tools to optimise the dynamic response performance.
The tool uses a linearized model of the power train and a system transfer function based on a sampled state-space model and the control loop design is fairly straight forward using standard control theory. In today’s digital control circuits, the regulator is often implemented as second-order digital filter. In such filters, the integrator section is fixed. So, the software tool is designed to define the placement of two zeros that fine-tune the loop and its total gain.
Integrated in the Ericsson DC/DC Power Designer software, the control-loop tool can be used in the design of the decoupling capacitance network by determining the type and number of capacitors and capacitance that is needed in order to meet the load transient requirements. Each decoupling capacitor is entered into the tool with capacitance and ESR, including tolerances. Tolerances are important because they define the ‘corners’ of the system that will determine the operating envelope of the digital controller. By entering these parameters, engineers can, in conjunction with the tool, minimise the number of decoupling capacitors needed for a certain load-transient requirement.
Fig. 2 – Capacitor description
Fig. 3 – Open loop Bode plot
The tool has been used in actual customer applications with good results. The example shows the improvements achieved using two paralleled Ericsson BMR464 POL regulators with optimized PID settings compared with the default settings.
Fig. 4 – Vout deviation with default PID settings and 5,000 µF
Fig. 5 –Dynamic response with optimized PID settings and reduced decoupling capacitance
The default wide-range control-loop algorithm that Ericsson POL regulators are delivered with is designed for robust and stable operation. Using the tool integrated in the Ericsson DC/DC Power Designer software it is possible for the power system designer to fine-tune the POL regulator’s control loop quickly and more easily than using manual techniques. The result is to significantly improve and optimize the dynamic response performance while keeping the required decoupling capacitance to a minimum.
