Embedding Technology for Ultra-fast Switching Power Electronics
Power semiconductors have undergone lots of advancements in the recent years, and new materials like SiC became ready for market. But also GaN devices come into play more and more, and even manufacturers of Si power chips squeeze out the possibilities of their devices, especially when it comes to switching speed, to be able to compete with SiC and GaN. Fast switching devices allow of course for high switching frequencies which, in turn, helps reducing passive devices like output chokes in active filters or solar inverters.
Power semiconductors have undergone lots of advancements in the recent years, and new materials like SiC became ready for market. But also GaN devices come into play more and more, and even manufacturers of Si power chips squeeze out the possibilities of their devices, especially when it comes to switching speed, to be able to compete with SiC and GaN. Fast switching devices allow of course for high switching frequencies which, in turn, helps reducing passive devices like output chokes in active filters or solar inverters.
Why a new packaging technology?
What fun is it to drive a Ferrari in the city? Traffic lights, traffic jams, bad streets and speed limits restrict the performance. A mid-range car is definitely sufficient for this task, and probably even better suited. But on a speedway, it’s totally different. So let’s build a speedway for our high speed switching power electronics.
Standard power electronics packaging uses a substrate like DCB or lead frame in e.g. TO housings, solders or sinters the chip onto it and connects the terminals on top of the chip with wire bonds. Parasitic inductances are a natural consequence, and they slow down switching speed and cause oscillations. Plus, unbalanced parasitic capacitances, e.g. output capacitance, induce earth currents and EMI problems.
The high switching frequencies that are offered by SiC and other wide band gap semiconductors can only be achieved if the package itself is optimized for this. So, the module has to be designed carefully. The approach shown in with applying the semiconductors on a DCB and do an embedding process on top has been refined. As a demonstrator to prove the benefit of high frequency switching and the achievement of low parasitics, an active filter against grid harmonics was chosen. Switching frequency is an order of magnitude higher than in conventional devices.
Package and semiconductor parasitics
The two following paragraphs deal with parasitic inductances and capacitances brought into the switching path by both the semiconductor and the package.
Semiconductor parasitics
Fig. 1: Parasitics coming from the semiconductor
Fig. 1 illustrates the parasitics coming from the semiconductor itself. Gate-drain (Cgd) and gate-source (Cgs) capacitances are responsible for the energy needed for reloading the gate. Gate resistance Rg slows down switching speed and causes additional losses when reloading the gate.
Package and switching cell parasitics
Fig. 2: a) Package parasitics, b) Switching cell parasitics
One step out of the semiconductor enables us to take a look at the parasitics coming from the package and the switching cell (Fig. 2). Both power and control current run through LS (Fig. 2 a). High gate inductivity Lg increases the gate path impedance, which can lead to parasitic switch on. Both parasitic inductances can cause ringing together with semiconductor capacitances.
Taking another step out leads us to the switching cell (Fig. 2 b)). Here, parasitics are generated by wires, traces, all kinds of conducting paths (Lσ and ESL (DC link inductance)) and by the assembly geometry and stack (Cσ). The DC link inductance slows down the switching speed and causes voltage overshoot. Cσout is reloaded with every switching event and originates an unwanted current into the heat sink, and if the two Lσ and the two Cσ are unbalanced, also they generate a current into the heat sink.
Module design
Fig. 3: a) Very Fast Switching module without spring contacts, b) CAD illustration
Knowing all the effects mentioned above, the following measures have been taken to achieve highest performance possible:
- One chip is flipped and the other one regularly sintered. Copper areas for DC+ and DC- potential on the DCB are the same size, so Cσ+ and Cσ- are the same size.
- Out potential is realized on the first PCB-layer and brought to the top layer by vias. This fact reduces output capacitance Cσout (s. Fig. 2 b)).significantly, because the Cu-ceramic-Cu stack no longer forms a capacitance connected to the heat sink which needs to be recharged with every switching event. Plus, the DCB-Cu acts as a shield.
- DC+ and DC- connection are located on the top layer, a first-stage DC-link and damping resistors are installed directly above the chips. Stray inductances Lσ, Ld and LS (see Fig. 2) are reduced significantly, because the loop is kept at the lowest profile possible and has broad tracks.
- Two driver boosters are installed on the module to ensure fastest switching possible. Thus, gate inductivity Lg is reduced and the gate capacitance can be charged or discharged very fast in case of a switching event. Additionally, LS is reduced and prevents the semiconductor of switching on at unwanted times.
- Electrical and mechanical connection to the driver board is realized with spiral springs, gate signals are transferred with spring contacts (see Fig. 3).
Manufacturing
Fig. 4: a) Silverpads, b) Sintered chips, c) Underfilled flip chip, d) Final module
The module is manufactured at Fraunhofer IZM in Berlin. Rogers manufactured the AlN-substrates with an etched 150µm step around the flipped chip. Selective silver pads are applied to the surface for silver sintering (Fig. 4 a)). In Fig. 4 b), the chips have been sintered onto the substrate and in Fig. 4 c) underfiller has been applied around the chip edges for both electrical isolation of the flip chip and protection of the sinter layer against braun acid, which is necessary for the following embedding process steps. Chip surface away from the DCB surface needs a copper metallization, which is clearly visible in Fig. 4 b) and c), to be connected with vias through the FR4. Fig. 4 c) shows the final module after the embedding process and mounting of connectors, snubber capacitances, damping resistors and boosters.
Measurement results
Fig. 5 a) shows the board for the driver, the power supply and the DC link for one phase. The embedded module shown in Fig. 5 b) is located on the bottom side directly under the CeraLink capacitor and pressed to the heat sink. The metal springs provide a high current capability and very low dc-link inductance. The plastic frame helps orienting and fixing the module and the spiral contacts between PCB and heat sink.
Fig. 5: a) Electrical driver test board for one half bridge b) Embedded module with electrical contacts, spiral contacts and plastic frame
For switching off, a booster function is implemented: The driver pulls the gate of the SiC chip down to -30 V for a very short time period of 10 ns. Afterwards, the gate is charged up to -6 V for static switch off. This feature enables a very fast turn off of the chip.
Some modules were also trialed power cycling. The internal body diode was used to correlate diode forward voltage USD to temperature. A calibration curve is recorded in an oven and during testing, this voltage is measured with a small measuring current of 100 mA. This gives the current junction temperature.
The MOSFET was heated up with 29A for 10s. A measuring current of 100 mA is sent through the body diode 400 µs after switch off, and the measured source-drain voltage gives the junction temperature in heated state. After another scarce 10 s, 300 ms before the next switch on, voltage is again measured in cooled down state. Termination criteria were TCase, max = 160°C and ΔImax = 10%. None of these occurred during the 100,000 cycles the test was run.
Conclusion
The technology is well suited for highly integrated and compact packaging of very fast switching power semiconductors, both wide bandgap and high speed silicon. Especially for wide bandgap devices, it is of high interest for the industry, because it enables engineers to use all the advantages of SiC and GaN and thus compensate the still higher semiconductor costs.
Acknowledgement
Thanks to Rogers for manufacturing and step etching the DCBs.
References
Hoene, E.; Ostmann, A.; The Lai, B.; Marczok, C.; Müsing, A.; Kolar, J.W.: Ultra-Low Inductance Power Module for Fast Switching Semiconductors, PCIM Europe, 14-16 May 2013, Nuremberg
Domurat-Linde, A.: Optimierung des Störemissionsverhaltens von Leistungsmodulen im UKW-Frequenzbereich, Pdh thesis, Technical University Berlin, 2013
Domurat-Linde, A.; Hoene, E.: Analysis and Reduction of Radiated EMI of Power Modules, Integrated Power Electronics Systems (CIPS), 2012 7th International Conference on , vol., no., pp.1-6, 6-8 March 2012
Hoffmann, S.: Reducing Inductor Size in High Frequency Grid Feeding Inverters, PCIM Europe, May 2015, Nuremberg
