Three Myths about Capacitors for Power Semiconductor Devices
Power electronics has evolved into a fast-developing field full of innovations that will have a great impact on our daily lives. One of the truly revolutionary developments in recent years is the TDK CeraLink™, a capacitor technology for the DC link or snubber based on piezo-ceramic material whose capacitance rises with increasing voltage and reaches its maximum value at its rated DC link voltage. Yet, despite the fact that power electronics is where the action is these days, a number of misconceptions about power semiconductor devices continue to persist, especially with regard to the problem of overshoot and the challenge of new, fast-switching semiconductors.
Power electronics has evolved into a fast-developing field full of innovations that will have a great impact on our daily lives. One of the truly revolutionary developments in recent years is the TDK CeraLink™, a capacitor technology for the DC link or snubber based on piezo-ceramic material whose capacitance rises with increasing voltage and reaches its maximum value at its rated DC link voltage. Yet, despite the fact that power electronics is where the action is these days, a number of misconceptions about power semiconductor devices continue to persist, especially with regard to the problem of overshoot and the challenge of new, fast-switching semiconductors.
Myth 1: There’s no elegant way to effectively reduce overshoot and ringing
Overshoot and ringing are common phenomena that occur during semiconductor switching. These unwanted effects contribute to higher power losses and heat generation or EMI problems. Designers are therefore well-advised to take adequate measures to prevent them. Semiconductor manufacturers recommend soft switching. This approach, however, can be counterproductive when using fast silicon IGBTs or even GaN- and SiC-based semiconductors. Especially with GaN and SiC the ringing is a direct result of the fast switching, and this requires additional EMI filtering, which, in turn, leads to additional losses and greater space requirements. According to conventional wisdom, it is nearly impossible to prevent overshoot without sacrificing compact and economical designs. That is, up until the introduction of the CeraLink.
Ceralink™ reduces overshoot and EMI (ringing) during turn-off
Our partners in the semiconductor industry have tested CeraLink thoroughly and determined that it is not only able to reduce the overshoot and the ringing to a large extent, but CeraLink can nearly eliminate the overshoot and ringing thanks to its extremely low ESL and ESR. If the capacitor is positioned correctly these unwanted effects nearly flatline. Designers have two basic options when it comes to positioning the CeraLink:
- In close proximity to the semiconductor as a DC link capacitor
- Directly on the terminals of a module as a snubber together with a standard external capacitor bank or optimally, even embedded inside the power module
The advantage of embedding the CeraLink directly inside the power module is that the necessary capacitance value is determined by the switching frequency and by the distance between the silicon die and the CeraLink – the closer the distance, the lower the inductance. It was found that a CeraLink with a value of between 0.25 and 2 µF works best and eliminates nearly all EMI caused by the ringing. As a result, module designers can take advantage of a high switching frequency and at the same time reduce the number of EMI components needed, thus finally lowering the total cost of solution.
Positioning a 1 to 20 µF CeraLink outside the semiconductor module is also a viable hybrid solution for designs that implement a DC link capacitor bank connected via a busbar or cables. In this case, CeraLink capacitors are connected in parallel to the capacitor bank where they are an ideal complement to the conventional capacitors. The capacitor bank provides the high capacitance values needed especially in industrial applications that work with the switching frequency, while the CeraLink minimizes voltage overshoot and reduces high frequency ringing in the kHz/MHz range caused by very high slew rates.
Myth 2: There’s no power capacitor that can work with GaN or SiC power modules
Some proponents of GaN or SiC claim that there is no power capacitor available that is able to support the high-speed switching of wide band gap technology. But when we demonstrated our CeraLink series they were surprised that the CeraLink can easily go with such a high speed.
CeraLink is also an enabler for emerging industrial applications such as inverters embedded in motors that are driven by the Ecodesign Directive 2009/125/EC. Because CeraLink is suitable for high ambient temperatures up to 150 °C peak, where other capacitor technologies fail, it is the DC link capacitor, even if the frequency of such inverters is normally below the target frequency of the CeraLink. Moreover, with its high capacitance density of up to 5.5 µF/cm³, CeraLink allows very compact designs.
Myth 3: CeraLink solutions are expensive
The price structure of CeraLink capacitors in mass production is comparable to that of conventional ceramic capacitors. CeraLink solutions can offer huge benefits in terms of total cost of ownership. Of course, each capacitor technology has its own set of unique strengths. Thanks to our broad portfolio of capacitor technologies for all kinds of inverters and power semiconductors, TDK can help designers find the right combination of capacitors for their particular application.
