Published July 11, 2016

Multichannel Programmable Power Controller Provides Efficient, Effective DC Rails

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The DC/DC power converter subsystems in today’s applications must provide flexibility and also support external control of many aspects of their operation as programmed by the user. Further, in designs with multiple supply rails – as most now are – there’s an increasing need for sophisticated management of the power conversion by a sophisticated controller IC and design tool, which will effectively support various converter combinations.

For this reason, programmable controllers for power conversion have been gaining in popularity, as they can provide the system design engineer with the required features and functions, along with ease of implementation.

This controller must implement three to four complete, independent pulse-width-modulated controllers including a light load mode for low power dissipation and high efficiency at low output currents. It also must provide a number of critical safety features, such as overcurrent protection (OCP), overvoltage Protection (OVP) and over temperature protection (OTP) plus input undervoltage lockout (UVLO). In addition, a number of key health-monitoring features are needed, such as warning-level flags for the safety functions and a power good (PGOOD) indication along with full monitoring of system voltages and currents. These functions are all programmable and/or readable from an SMBus and many are steerable to the GPIO ports for hardware monitoring by the system controller.  Of course, all this must be housed in a small package for space efficiency.

Required Feature Set

The list of desired controller features is extensive and illustrates how much the design engineer now expects the selected controller to do. The Exar XRP7724 quad-channel digital PWM/PFM programmable power management system (Figure 1) meets these many requirements including:

• Supporting a wide switching frequency range, with independent, programmable channel-to-channel constant operating frequency;
• Each channel is configurable for soft-start and soft-stop sequencing, including delay and ramp control;
• Low standby/light load power consumption, with an ultrasonic mode to limit the audible noise emanating from inductor;
• Integrated MOSFET drivers that can drive a wide range of input gate-source capacitance values (C_gs);
• Programmable five-coefficient PID control which, together with the output capacitor, allows the designer to fine tune the control loop for best transient response;
• A wide input/output voltage range;
• SMBus compliant – operations fully controlled via a I²C interface, allowing for advanced local and/or remote reconfiguration, full performance monitoring and reporting, as well as fault handling;
• And of course, a full set of safety- and fault-related features (as discussed earlier)

Fig 1: The simplified schematic of XRP7724 a quad-channel programmable controller shows the level of complexity and features incorporated in the IC. (click to zoom)

Controller Architecture

The functional block diagram of the regulation loops for an output channel, Figure 2, shows the four separate, parallel control loops: pulse width modulation (PWM), pulse frequency modulation (PFM), ultrasonic and oversampling (OVS). Each of these loops is fed by the analog front end (AFE) at the left of the diagram. The AFE consist of an input voltage-scaling function, programmable voltage reference DAC, error amplifier and window comparator. 

Fig 2: The XRP7724 regulation loops shows the four separate, parallel control loops within the device. (click to zoom)

To provide current level information, the output inductor’s current is measured by a differential amplifier that reads the voltage drop across the on-resistance (RDSON) of the lower MOSFET during its "on" time. This voltage is converted to a digital value by the current ADC block and the resulting current value is used to determine when PWM-to-PFM mode transitions should occur, see sidebar "PWM- and PFM-mode control loops."

Transient Response

When powering CPU and digital-power modules, transient response is of the utmost importance, Figure 3 and Figure 4. That is where oversampling mode is most effective, so this feature was added to the XRP7724 to improve transient responses. In OVS mode, the output voltage is sampled four times per each switching cycle and is monitored by the AFE window comparator. If the voltage goes outside the set high or low limits, the OVS control electronics can immediately modify the pulse width of the high-side or low-side gate drivers to respond accordingly without having to wait for the next cycle to start. OVS has two types of responses, depending on whether the high limit is exceeded during an unloading transient (overvoltage) or the low limit is exceeded during a loading transient (undervoltage).

 

Fig. 3: The XRP7724 has excellent response for a 0A to 6A load transient, when operating at 300 kHz in PWM mode only.

 

Fig. 4: The 10-to-6 A transient response at 300 kHz with OVS set at ±5.5% shows further improvement.

PowerArchitect 5.0

In addition to a high-performance, function- and feature-rich IC, it is critical to have a user-friendly GUI (graphical user interface) to simplify fine tuning of the control-loop parameters for optimum performance. For maximum flexibility and to allow the system designer total control over the implementation and performance, Exar offers PowerArchitect™ 5.0, a sophisticated design tool which accelerates the selection of the power-train components including output inductors and capacitors, as well as the control loop design. The tool generates a Bode plot based on the user’s choices for the five programmable coefficients of the PID control in the XRP7724, as well the choice of switching frequency, output voltage and current. The user can either accept it or can modify the PID parameters to suit the requirements of the design.

The GUI screen, Figure 5, shows the selected switching frequency, output filter inductance and capacitance, PID coefficients, Bode plot and phase margin, along with the control loop bandwidth for channel 1. All of the related parameters are under the user’s control to fine tune or even change completely for easy, immediate investigation of “what if?” scenarios.

 

Fig. 5: PA5.0 The GUI screen of Exar’s PowerArchitect™ 5.0, a sophisticated design tool which shows all the selected and calculated parameters and allows users to fine-tune the design and response to meet the tradeoffs among their many requirements.

Sidebar: PWM- and PFM-mode control loops

The PWM control loop operates in voltage-control mode with optional input voltage feedforward. To obtain a full output voltage range for best effective resolution, an input scaler is used to reduce the feedback voltage of these higher output voltages, thus bringing them down to the reference voltage’s control range. The error voltage is converted to a digital error term by the AFE ADC. The error register has a fine-adjust function that can be used to improve the output voltage’s set-point resolution by a factor of five, resulting in low-, mid- and high-range resolution of 2.5 mV, 5 mV and 10 mV, respectively. The proportional integral derivative (PID) controller output uses the error resistor’s voltage to manage the loop dynamics.

The controller has a PFM loop that can be enabled to improve efficiency at light loads. Reducing the switching frequency and operating in the discontinuous conduction mode (DCM) minimizes both switching and conduction losses. The PFM loop works in conjunction with the PWM loop and is entered when the output current falls below a user-programmed threshold level for a programmed number of cycles. The PWM loop is disabled In PFM mode; instead, the scaled output voltage is compared to reference voltage using a window comparator.

In PFM mode, when the high-side FET is turned on, the inductor current ramps up and this charges the output capacitors and increases their voltage. After the completion of the high-side and low-side on-times, the lower FET is turned off to inhibit any reverse-current flow through the inductor. The load current then discharges the output capacitors until the output voltage falls below the reference voltage and the comparator is activated, which triggers the digital PWM function to start the next switching cycle. The time from the end of the switching cycle to the next trigger is referred to as the dead zone.  This PFM technique ensures output-voltage ripple does not increase from PWM to PFM.

The switching duty cycle is the same as it was in PWM mode when PFM mode is entered initially. This causes the inductor’s ripple current to be at the same level as it was in PWM mode. The PFM duty cycle is calculated based on the ratio of the output voltage to the input voltage. If the output voltage ever goes outside the high/low windows, the controller exits the PFM mode and reactivates the PWM loop.

Although the PFM mode does a good job of improving efficiency at light load, the dead-zone time can increase at very light loads to the point where the switching frequency can be within the audio hearing range. When this happens, some components – such as the output inductor and ceramic capacitors – can emit audible noise which may be annoying to users. The amplitude of the noise depends mostly on the board design as well as the manufacture and construction details of the components. Proper selection of components can reduce the sound to very low levels. In general, ultrasonic mode is not used unless required, as it reduces efficiency at very light loads.