Published April 11, 2016

An Active Solution to Dependable FPGA Power Sequencing

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Ensuring the correct turn-off sequence for multiple FPGA power rails is as important as the power-up procedure, to prevent undetermined voltage states leading to early device failure.

Power Sequencing for Safety’s Sake

Several techniques are possible for controlling the sequence and timing when starting up multiple power rails for today’s large System-on-Chip FPGAs. Observing the correct sequence, as specified by the device manufacturer, is important to prevent the device drawing excessive current and becoming damaged as a result.

Some approaches are to manipulate each converter’s Power-good output to control the Enable pin of the next supply in the sequence. A capacitor can be inserted if a delay is required. A similar method is to use a reset IC to start the next converter when the preceding supply has reached a satisfactory voltage. Each approach has some drawbacks, and neither is able to control the power-down sequence. Powering down the rails in the correct reverse sequence is just as important as the power-up sequence to ensure safe device operation.

Using a dedicated power-sequencing IC provides a more reliable way to ensure the correct sequence. The IC can be programmed to send each enable signal at a desired time. Figure 1 shows how a multi-channel sequencer can manage FPGA core-logic, peripheral and I/O power domains. Even so, the power-down sequence remains difficult to control, because the decoupling capacitors on each power rail can hold residual charge for an indeterminate time after the converter is turned off. As much as 20mF of total decoupling capacitance can be connected to each rail.

 

Figure 1. Managing FPGA power rails with a sequencing IC.

Controlling Power-Down

Actively discharging the decoupling capacitors using a circuit that has a known time constant enables the sequencer to maintain the correct power-down sequence. This can be achieved by temporarily inserting a discharge resistor in series with the capacitor. Figure 2 shows how a resistor can be switched into the circuit using a pair of carefully chosen MOSFETs with minimal additional components required.

The power sequencer’s EN output is connected to the enable pin on the DC-DC regulator, and also to the gate of the P-channel MOSFET (Q1). When the sequencer output goes low to disable the DC DC regulator, Q1 inverts the signal thereby turning on the N-channel MOSFET Q2. When turned on, Q2 discharges the 15mF decoupling capacitor to ground through the resistance R2.

Figure 2. Active-discharge circuit for controlled power sequencing.

The circuit shown assumes the DC-DC regulator cannot continue producing an output once the shutdown signal is applied. If the DC-DC regulator’s output can continue supplying power after receiving the shutdown command, an extra delay is needed before the discharge circuit is activated.

The value of R2 is chosen to ensure a suitable discharge time allowing the sequencer to complete the power-down within an acceptable time period. Note also that the resistance should be large enough to prevent sharp rising current peaks that could cause EMI issues and impose transient thermal stresses on both Q2 and the decoupling capacitor bank. In practice, the value of R2 is chosen after considering additional important parameters such as the on-resistance (R_DS(ON)) of Q2 and the equivalent series resistance (ESR) of the capacitor bank.

The MOSFET Q1 should be selected by referring to the output voltage threshold of the power-sequencer. The selected device should have a high enough gate threshold voltage (V_GS(th)) to ensure it remains turned off when the sequencer output is high, bearing in mind that V_GS(th) falls with increasing junction temperature. The chosen sequencer for this example operates from a 5V supply, and has minimum specified high-level output voltage of 4.19V. The V_GS(th) of Q1 must be greater than 0.9V at the ambient operating temperature of 60°C to ensure correct operation. Moreover, the gate should be pulled down to source potential using a 100kΩ resistor to avoid false turn-on. Checking the normalised curves for V_GS(th) versus temperature in the MOSFET datasheet shows that the Diodes Inc. ZXMP6A13F meets the requirements: the guaranteed minimum V_GS(th) is 1V at room temperature, falling to about 0.9V at 60°C.

For the purposes of this example, we shall assume that the sequencer must turn off a total of 10 voltage rails within 100ms. Hence, the decoupling-capacitor bank on each rail must be discharged in less than 10ms. Aiming for a 3x RC time constant of 8ms ensures that the capacitor is discharged below 5% of its full voltage within the required time. To calculate the RC constant, the MOSFET R_DS(ON), parasitic trace resistances and ESR of the capacitor bank must be considered, together with the resistor R2.

Assuming the capacitor ESR and trace resistances combined are no greater than 10mΩ, and the total decoupling bank capacitance is 15mF, suitable values for R_DS(ON) and R2 can be calculated from the expression:

3 x (10mΩ + R2 + (1.5 x R_DS(ON))) x 15mF = 8ms

Assuming R2 = 50mΩ, the Power MOSFET Q2 must have R_DS(ON) less than 80mΩ at V_GS = 4.5V and ambient temperature of 25°C.

When selecting the MOSFET, the effect of temperature-related change and lot-to-lot variation of R_DS(ON) should also be considered. R_DS(ON) can vary by as much as 15mΩ over the expected operating temperature range at 4.5V gate drive. Hence it is best to ensure that R2 is about double the manufacturer-specified maximum R_DS(ON) of the chosen MOSFET. If R2 is to be 50mΩ, a MOSFET such as the Diodes Inc. DMN3027LFG N-channel MOSFET can be selected. This device has typical and maximum R_DS(ON) of 22mΩ and 26.5mΩ respectively at V_GS = 4.5V, at room temperature. Hence, R_DS(ON) can vary from about 15mΩ to 40mΩ, giving 95% (3x RC) discharge time between 3.9 to 5.4ms with a worst case capacitor bank size of 20mF.

Is the MOSFET Tough Enough?

Because the DMN3027LFG will dissipate the capacitor’s energy as a function of both current and voltage over time, it is necessary to assess the maximum single pulse that the Power MOSFET can safely handle whilst ensuring the junction temperature does not exceed the absolute maximum rating, typical T_J(max) = 150°C. This can be seen by inspecting the Safe Operating Area (SOA) in the MOSFET datasheet. The SOA should be based on the application’s ambient operating temperature with the required MOSFET gate drive. In the case of discharging the 0.9V charged capacitor bank, an acceptable SOA curve should indicate single-pulse peak current capability of at least 1V for pulse widths between 1ms and 10ms. The SOA should be for a typical application ambient temperature, which is assumed to be 60°C, whilst mounted on a PCB with minimal heatsinking, otherwise known as minimum recommended pad (MRP) layout.

It is also necessary to consider the power dissipation in both the DMN3027LFG (Q2) MOSFET and the series resistor R2. The worst case scenario will be caused by charging and discharging the capacitor for short periods of time. Assuming, as a worst case, that the power sequencer could enter a continuous loop enabling and then disabling the DC-DC regulator every 20ms (10ms enable + 10ms disable), about 0.5W would be dissipated across the DMN3027LFG and R2. This is calculated by knowing the total energy stored in the capacitor bank will be discharged every 20ms:

P = E ÷ t = ½CV² ÷ 20ms = 500mW (assuming C = 20mF charged to 1V)

Since the maximum temperature-adjusted R_DS(ON) of the DMN3027LFG is 40mΩ, the power dissipation in Q2 and R2 is 222mW and 278mW, respectively. At the lowest R_DS(ON) of 15mΩ, the power dissipation in R2 would increase to 385mW. Hence a resistor of 0.5W rating is required.

In the typical application, the ambient temperature is expected to reach 60°C and the DMN3027LFG has junction-to-ambient thermal resistance (R_θJA) 130°C/W on minimum recommended pad layout, then T_J reaches 90°C when dissipating 222mW. This gives plenty of headroom from the T_J(max) = 150°C.

Figure 3 shows how the circuit performs in practice. The peak current is limited to about 12.5A and the time to discharge the capacitor bank to 5% of its initial 1V charged state is about 4ms, which is close to the figure calculated from theoretical values.

Figure 3. Power-down of a single rail within controlled time and limited discharge current.

Conclusion

Powering down individual power-supplies in the correct order is as important as ensuring the correct power-up sequence, for preventing damage to complex multi-rail FPGAs. Actively discharging decoupling capacitors provides a reliable means of ensuring each power rail is turned off within a known time. The components of the active-discharge circuitry, predominantly the series resistor and main MOSFET switch, should be selected to ensure a suitable time constant and withstand the stresses that could be imposed during worst-case power-cycling conditions.