Digital Power

Three-Phase PWM IP Core for Intel MAX 10 FPGAs

Alizem announced the release of its new 3-phase pwm IP Core optimized for Intel® MAX® 10 FPGAs and designed to be used in 3-phase inverter power electronics applications such as industrial pump control, solar power conversion and power supplies.

This software product helps engineers design better products, faster by enabling engineers to spend their resources on their true product differentiation features rather than reinventing the wheel on the development of 3-phase pwm logic and its associated software drivers. At less than 100 LEs per axis, the IP has very small footprint and fits on the smallest Intel MAX 10 FPGA.

Features include:

  • Tunable PWM frequency from 500 Hz to 100 kHz @50 MHz clock
  • Adjustable deadtime to prevent shoot-through faults and maximize efficiency.
  • Voltage reference either in V(a,b,c) or V(alpha,beta) spaces.
  • Integrated sine & cosine functions for V(alpha,beta) to V(a,b,c) conversion.
  • 16 bits electrical resolution.
  • Test mode to validate correct pwm function before connecting load.

"PWM is the first design block of every power electronics systems since it is meant to generate signals triggering the commutation of inverter's power transistors. It has to maximize phase voltage output quality while also protecting the inverter against shoot-through faults with proper deadtime settings," said Dr. Marc Perron, president at Alizem.

Block Diagram (click on image to enlarge)

"While this is basic knowledge for a typical power electronics engineer, this is not that easy for embedded systems engineers involved in the design of electronic products driving 3-phase inverters often packaged into COTS intelligent power modules (IPM). However, both can benefit from the costs, risks and time-savings of using Alizem 3-phase pwm IP Core in their design and focus on their true product value and differentiation features," concluded Dr. Perron.

Alizem ships its 3-phase pwm IP Core as a QSys component and its software drivers and API running on a NIOS® II processor. It is packaged with a reference design based around the Intel MAX 10 FPGA development kit and PMOD Dual H-Bridge components.

Four different versions are offered combining different sets of software and licensing options: (1) demo version for early prototypes, (2) low-volume version for designs targeting niche and specialized products of less than 1k units per year, (3) high volume version for production of less than 10k units per year and (4) unlimited source code version for those looking for a code base and work from there.

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