PMIC with 1A Li+ Linear Battery Charger for Low-Power Processor Systems

The PF1550 from NXP is a power management integrated circuit (PMIC) designed specifically for use with i.MX processors on low-power portable, smart wearable and Internet-of-Things (IoT) applications. It can provide full power solution to i.MX 7ULP, i.MX 6SL, 6UL, 6ULL 6SX and RT processors-based, battery-powered systems.

With 1A integrated Li+ three high-efficiency buck converters, three linear regulators, DDR reference and RTC supply, the PF1550 can provide power for a complete system, including application processors, memory, and system peripherals.

The PF1550 features low quiescent current to maximize battery life and is available in power efficient, space-saving 5x5mm QFN package. It is available in two temperature grades, industrial with an operating temperature range of -40 to +105 degrees C and consumer with an operating temperature of -40 to +85 degrees C.

Examples of anticipated applications include: access control panels, connected devices, E-read, POS, industrial control and home automation, IoT gateways, smart appliances, and smart wearable/mobile devices.

Detailed description

The PF1550 PMIC features three high efficiency low quiescent current buck regulators, three LDO regulators, a DDR voltage reference to supply voltages for the application processor and peripheral devices.

Additionally, PF1550 incorporates a single cell Li-ion linear battery charger with a USBPHY regulator. The buck regulators provide the supply to processor cores and to other low voltage circuits such as I/O and memory. Dynamic voltage scaling is provided to allow controlled supply rail adjustments for the processor cores for power optimization.

The three LDO regulators are general purpose to power various processor rails, system connectivity devices and/or peripherals. Depending on the system power configuration, the general purpose LDO regulators can be directly supplied from the main system supply VSYS or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN.

(click on block diagram to enlarge)

A specific VREFDDR voltage reference is included to provide accurate reference voltage for DDR memories operation. The VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS (Secure Non-Volatile Storage) /RTC (Real Time Clock) circuitry on the processor.

VSNVS is powered from VSYS or from a coin cell. To accommodate applications that do not include Li-ion battery, the PF1550 battery charger regulates the input voltage at VBUSIN pin down to maximum of 4.5 V at VSYS through the power path circuit.

Summary of features and specifications:

  • Input voltage VIN from 5V bus, USB, or AC adapter (4.1 V to 6.0 V) withstands up to 22V transient
  • Linear 1A Li+ Battery Charger
  • Buck converters:
    • SW1, 1.0 A; 0.6 V to 1.3875V
    • SW2, 1.0 A; 0.6 V to 1.3875V
    • SW3, 1.0 A; 1.8 V to 3.3 V
  • LDO regulators
    • LDO1, 0.75 to 1.5 V/1.8 to 3.3 V, 300 mA with load switch mode
    • LDO2, 1.8 to 3.3 V, 400 mA
    • LDO3, 0.75 to 1.5 V/1.8 to 3.3 V, 300 mA with load switch mode
  • LDO/switch supply
  • RTC supply VSNVS 3.0V, 2.0mA
  • Coin Cell Charger
  • DDR memory reference voltage, VREFDDR, 0.5 to 0.9V, 10mA
  • I2C interface
  • User programmable Standby, Sleep/Low-power, and Off (REGS_DISABLE) modes
  • Ambient temperature range −40°C to 105°C
NXP Semiconductors N.V.
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