Communications Power

Multi-Rail Power Sequencer and Monitor IP Blocks Reference Design

The Multi-Rail Power Sequencer and Monitor reference design from Intel Corp. is a highly parameterizable set of IP blocks that can be customized to meet specific power sequencing needs. It controls the enable sequence of up to 143 output rails, can be distributed across multiple Intel® MAX® 10 devices to increase the number of monitored channels, and can draw from a mixture of Power Good (POK) inputs as well as monitored voltage rails.

The sequencing can be based on voltages reaching a certain threshold as well as timed events, it offers parameterizable levels of glitch filtering on POK or voltage inputs, customizable retry responses, a comprehensive PMBus interface, and numerous other options to tailor the sequencer to the needs of your application.

Architecture and Operation

Electronic systems containing FPGAs, CPUs, DSPs and ASICs require specific sequences for the power to be applied to and removed from those devices. The Multi-Rail Power Sequencer and Monitor provides the ability to monitor and correctly sequence up to 144 rails (including monitoring VIN) through normal as well as errored conditions. It accepts any combination of analog voltage and digital Power Good inputs, and maps any ADC input or Power Good signal as any monitored VOUT or VIN rail.

These remapped and decoded inputs are passed to the “Sequencer Voltage Monitor” block, which checks and reports the status for power good, undervoltage, overvoltage, alarms, present voltage levels, and so on. The power sequencer design implements a sequential approach when powering up the rails, and powers them down in the reverse order. Information regarding the state of the various rails is provided to the PMBus slave interface.

PMBus is a protocol that operates on the I2C physical interface. It is compliant with the PMBus specification revision 1.3.1 and is capable of operating at both 100KHz and 400KHz modes. The output of the “Sequencer Voltage Monitor” block provides the status used by the “Power Sequencer” block, for enabling and disabling the various power rails.

Since the functionality is partitioned into multiple blocks, the user can easily remove any blocks that might not be needed, customizing the sequencer to fit their needs in the most cost-effective implementation. When only a simple sequencer which bases its control on the state of the POK signals is needed, the “Power Sequencer” block (shown below, in the green-shaded area of the figure below) can be used without any of the other blocks. If voltage rails are being monitored, but PMBus support is not required, the PMBus slave block (shown in the yellow-shaded area of the figure below) can be removed.

Power Sequencer Design Blocks

Features:

  • Sequence and monitor any combination of up to 144 rails
  • Up to 18 voltage-monitored rails per Intel® MAX® 10 device
  • Up to 144 digital-monitored (POK) rails per Intel® MAX® 10 device
  • Monitor overvoltage, undervoltage, and power good status
  • Easily configurable via Platform Designer GUI
  • PMBus* 1.2 compliant slave interface
  • Programmable noise filtering on analog input samples
  • Programmable debouncing (28 delay levels) of digital power good inputs
  • Latch all warning and fault conditions until cleared
  • Set defaults and dynamically control levels for overvoltage, undervoltage, and power good
  • Programmable response behavior for overvoltage and undervoltage events
  • Configurable delays between sequencing of rails, qualification window, discharge, and retries
  • Can be cascaded or instantiated multiple times within the same device as independent controllers
  • Includes simulation test bench to predict behavior
Intel Corp.
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