Moortec delivered its In-Chip Monitoring solution on TSMC 7nm FinFET process to the new Arm® Neoverse™ N1 System Development Platform (SDP). Moortec supported the integration and utilization of its process, voltage, and temperature (PVT) sensing subsystem technology for the platform, which is intended to enable Arm Neoverse solutions for next-generation cloud-to-edge infrastructure.
Moortec says that Neoverse N1 SDP is the first 7nm infrastructure-specific system development platform that enables asymmetrical compute acceleration through the CCIX interconnect architecture. The Moortec and Arm collaboration achieved a solution that can dynamically sense in-chip conditions to aid power consumption optimization, maximize system speed, and enhance device reliability.
Within the fabric of the Moortec embedded in-chip monitoring subsystem, the Process Monitor lets advanced node Integrated Circuit (IC) developers detect the process variation of core digital MOS devices.
The Process Monitor can be used to enable continuous Dynamic Frequency and Voltage Scaling (DVFS) optimization systems, gate delay measurments, monitoring of manufacturing variability across chip, critical path analysis, critical voltage analysis, and also monitoring of silicon ‘ageing’.
The subsystem also features a Voltage Monitor which is a low power self-contained IP block that Moortec specially designed to monitor voltage levels within the core logic voltage domains and deliver accurate IR drop analysis. The company customizes the measurement range to suit each technology. The Voltage Monitor IP can also monitor analog (IO) supply domains and is also well-suited for monitoring supply droops and perturbations.
A high-precision, low power junction temperature sensor completes the system, which Moortec developed to be embedded into ASIC designs.
The PVT subsystem also includes an advanced PVT Controller with AMBA APB interfacing, which supports multiple monitor instances, statistics gathering, a production test access port, and other compelling features.
The Neoverse N1 SDP is available to hardware and software developers for hardware prototyping, system validation, software development, and performance tuning and profiling.
“Arm Neoverse solutions are designed to deliver the performance and efficiency required to enable the cloud-to-edge infrastructure for a world with a trillion connected devices,” said Mohamed Awad, vice president of marketing, Infrastructure Line of Business, Arm. “Our collaboration with Moortec on the N1 SDP test chip demonstrates how another piece of validated IP fits within the Neoverse platform, accelerating development and adoption of Arm-based solutions across the infrastructure.”
“Through our collaboration, we are helping to enhance performance and efficiency of Arm’s next-generation compute technology on 7nm. By contributing our high accuracy embedded sensing fabric to the development of the Neoverse N1 SDP, we’re enabling customers to benefit from higher performance and reliability within machine learning, artificial intelligence and data analytics applications,” said Moortec CEO, Stephen Crosher.