New Industry Products

High Speed 650V Half-Bridge Driver for GaN Power Switches

July 25, 2019 by Paul Shepard

The NCP51820 high−speed, gate driver from ON Semiconductor is designed to meet the stringent requirements of driving enhancement mode (e−mode), high electron mobility transistor (HEMT) and gate injection transistor (GIT), GaN power switches in off−line, half−bridge power topologies.

The NCP51820 offers short and matched propagation delays with advanced level shift technology providing −3.5V to +650V (typical) common mode voltage range for the high−side drive and −3.5V to +3.5V common mode voltage range for the low−side drive. In addition, the device provides stable dV/dt operation rated up to 200V/ns for both driver output stages in high speed switching applications.

Typical Applications:

  • Driving GaN Power Transistors used in Full or Half−Bridge, LLC, Active Clamp Flyback or Forward, Totem Pole PFC and Synchronous Rectifier Topologies
  • Industrial Inverters and Motor Drives
  • AC-DC Converters

To fully protect the gate of the GaN power transistor against excessive voltage stress, both drive stages employ a dedicated voltage regulator to accurately maintain the gate−source drive signal amplitude. The circuit actively regulates the driver's bias rails and thus protects against potential gate−source over−voltage under various operating conditions.

The NCP51820 offers important protection functions such as independent under−voltage lockout (UVLO), monitoring VDD bias voltage and VDDH and VDDL driver bias and thermal shutdown based on die junction temperature of the device. Programmable dead−time control can be configured to prevent cross−conduction.

Summary of Features

  • 650V, Integrated High−Side and Low−Side Gate Drivers
  • UVLO Protections for VDD High and Low−Side Drivers
  • Dual TTL Compatible Schmitt Trigger Inputs
  • Split Output Allows Independent Turn−ON/Turn−OFF Adjustment
  • Source Capability: 1A; Sink Capability: 2A
  • Separated HO and LO Driver Output Stages
  • 1ns Rise and Fall Times Optimized for GaN Devices
  • SW and PGND: Negative Voltage Transient up to 3.5V
  • 200V/ns dV/dt Rating for all SW and PGND Referenced Circuitry
  • Maximum Propagation Delay of Less Than 50ns
  • Matched Propagation Delays to Less Than 5ns
  • User Programmable Dead−Time Control
  • Thermal Shutdown (TSD)