Components

Dual- and Single-Core DSCs for Motor Control & High-Density DC-DCs

Microchip Technology Inc. announced new dual- and single-core dsPIC33C Digital Signal Controllers (DSCs) with more options to meet changing application requirements across memory, temperature, and functional safety. The company’s new dsPIC33CH512MP508 dual-core DSC enables support for applications with larger program memory requirements. The dsPIC33CK64MP105 single-core DSC adds a cost-optimized version for applications that require smaller memory and footprint. According to Microchip, the new devices are pin-to-pin compatible within the dsPIC33CH and dsPIC33CK families, allowing developers to scale easily across product lines.

This compact device is suitable for motor control, automotive sensors, high-density dc-dc applications, or stand-alone Qi transmitters.

Microchip’s dsPIC33CH family of DSCs feature dual 90 & 100 MIPS 16-bit dsPIC® cores with integrated DSP and enhanced on-chip peripherals. The company says that these DSCs enable the design of high-performance, precision motor control systems that are more energy efficient, quieter in operation and provide extended motor life. The dsPIC33CH DSCs can be used to control BLDC, PMSM, ACIM, SR and stepper motors. These DSCs can also enable the design of switched mode power supplies such as ac-dc, dc-dc, UPS, and PFC, providing high-precision digital control of buck, boost, fly-back, half-bridge, full-bridge, LLC and other power circuits to achieve the highest possible energy efficiency.

The dsPIC33CH512MP508 (MP5) family expands the recently introduced dsPIC33CH with Flash memory growing from 128KB to 512KB and it triples the program RAM from 24KB to 72KB. This Flash and RAM expansion enables support for larger applications with multiple software stacks or larger program memory, such as automotive and wireless charging applications. Microchip notes that more memory is needed to accommodate AUTOSAR software, MCAL drivers, and CAN FD peripherals in automotive applications.

Features of dsPIC33CH Family
Operating Conditions
  • 3V to 3.6V, -40°C to +125°C
Core: Dual 16-Bit dsPIC33CH CPUs
  • Master Core 90 MIPS and Slave Core 100 MIPS Operation
  • Independent Peripherals for Master Core and Slave Core
  • Configurable Shared Resources for Master Core and Slave Core
  • Fast 6-Cycle Divide
  • Message Boxes and FIFO to Communicate Between Master and Slave (MSI)
  • Code Efficient (C and Assembly) Architecture
  • 40-Bit Wide Accumulators
  • Single-Cycle (MAC/MPY) with Dual Data Fetch
  • Single-Cycle, Mixed-Sign MUL Plus 6-Cycle Hardware Divide
  • 32-Bit Multiply Support
  • Five Sets of Interrupt Context Selected Registers and Accumulators per Core for Fast Interrupt Response
  • Zero Overhead Looping
High-Performance Peripherals for Real-Time Control
  • 4 x 12-bit 3.5 MSPS ADCs: 34 Channels
  • High Speed PWMs with 250ps resolution, 12×2 Channels
  • Optimized for high-performance digital power, motor control and applications requiring sophisticated algorithms
Master Core Features
  • Core Frequency 90 MIPS @ 180MHz
  • Program Flash: 512KB/256KB Dual Partition with LiveUpdate
  • Data RAM: 48KB/32KB
  • 16-Bit Timer: 1
  • DMA: 6
  • SCCP (Capture/Compare/Timer): 8
  • UART: 2
  • SPI/I2S: 2
  • I2C: 2
  • CAN Flexible Data-Rate (FD): 2 (’50x devices only)
  • SENT: 2
  • CRC: 1
  • QEI: 1
  • PTG:1
  • CLC: 4
  • 16-Bit High-Speed (250ps) PWM: 4×2
  • 12-bit, 3.5 Msps ADC: 1, 16 Channels
  • Digital Comparator: 4
  • 12-Bit DAC/Analog CMP Module: 1
  • Watchdog Timer: 1
  • Deadman Timer: 1
  • Breakpoints: 3 complex, 5 simple
  • Oscillator: 1
Slave Core Features
  • Core Frequency 100 MIPS @ 200 MHz
  • Program Memory: 72KB(PRAM) Dual Partition with LiveUpdate
  • Data RAM: 16KB
  • 16-Bit Timer: 1
  • DMA: 2
  • SCCP (Capture/Compare/Timer): 4
  • UART: 1
  • SPI/I2S: 1
  • I2C: 1
  • QEI: 1
  • CLC: 4
  • 16-Bit High-Speed (250ps) PWM: 8×2 Channels
  • 12-bit, 3.5 Msps ADC: 3, 18 Channels
  • Digital Comparator: 4
  • 12-Bit DAC/Analog CMP Module: 3
  • Watchdog Timer: 1
  • Deadman Timer: 1
  • Breakpoints: 1 complex, 2 simple
  • Oscillator: 1
Clock Management
  • Internal Oscillator
  • Programmable PLLs and Oscillator Clock Sources
  • Master Reference Clock Output
  • Slave Reference Clock Output
  • Fail-Safe Clock Monitor (FSCM)
  • Fast Wake-up and Start-up
  • Backup Internal Oscillator
  • LPRC Oscillator
Power Management
  • Low-Power Management Modes (Sleep, Idle, Doze)
  • Integrated Power-on Reset and Brown-out Reset
  • Debugger Development Support
  • In-Circuit and In-Application Programming
  • Simultaneous Debugging Support for Master and Slave Cores
  • Master Only Debug and Slave Only Debug Support
  • IEEE 1149.2 Compatible (JTAG) Boundary Scan
  • Trace Buffer and Run-Time Watch

Implementing wireless charging in automotive applications requires additional software stacks for the Qi protocol and Near-Field Communication (NFC), driving the need for even more program memory. Live Update capability enables real-time firmware updates for high-availability systems, but it also doubles the overall memory requirement.

In the dual-core devices, one core can function as a master while the other operates as a slave. The slave core is useful for executing dedicated, time-critical control code while the master core is busy running the user interface, system monitoring, and communications functions. For example, having two cores aids the partitioning of the software stacks for parallel execution of the Qi protocol and other functions including NFC to optimize performance in automotive wireless charging applications.

The dsPIC33CK64MP105 (MP1) family extends the recently introduced dsPIC33CK family with a cost-optimized version for smaller memory and footprint applications, offering up to 64KB Flash memory and 28- to 48-pin packages.

Features of dsPIC33CK Family
Operating Conditions
  • 3.0V to 3.6V, -40ºC to +125ºC, DC to 100 MIPS
dsPIC33CK DSC Core
  • Up to 64KBytes of Program Flash with ECC
  • Up to 8KBytes of Data SRAM with Memory Built-in Self-Test (MBIST)
  • Modified Harvard architecture with 16-bit data and 24-bit instructions
  • Code efficient (C and Assembly) CPU architecture designed for real-time applications
  • Sixteen 16-bit working registers
  • 4 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling
  • Single-cycle, mixed-sign 32-bit MUL
  • Fast 6-cycle hardware 32/16 and 16/16 DIV
  • Dual 40-bit fixed point Accumulators (ACC) for DSP operations
  • Single-cycle MAC/MPY with dual data fetch and result write-back
  • Zero overhead looping support
High-Speed PWM Module
  • 4 independent PWM pairs (8 total outputs) with up to 250ps resolution
  • Dead-time insertion for rising and falling edges and dead-time compensation support
  • Clock chopping for high-frequency operation
  • Fault and current limit inputs
  • Flexible trigger configuration for ADC triggering
Advanced Analog Features
  • 3 12-bit 3.5 MSPS ADC Modules each with 2 dedicated SARs and 1 shared SAR cores (3 S&Hs)
  • 12, 16, 19 ADC input channels (depending on package)
  • 4 digital comparators for reducing CPU overhead
  • 4 oversampling filers up to 256x for increased resolution (up to 16-bits)
  • 3 analog comparators (15ns) with dedicated 12-bit DACs with hardware slope compensation
  • Up to 3 op amps with internal connection to ADC Module
Timer/Counters/Output Compare/Input Capture
  • 11 16-bit timer/counters (up to 5 32-bit)
  • 4 SCCP
  • 1 MCCP
  • 10 PWM outputs
  • Peripheral Trigger Generator (PTG) for scheduling complex sequences
  • 2 Quadrature Encoder Interface (QEI) Modules for optical encoder support
Communication Interfaces
  • 3 UARTs (15 Mbps) with automated protocol handling for LIN/J2602, DMX and IrDA®
  • 3 4-wire SPI/I2S up to 40 MHz with dedicated pins
  • 2 I2C Modules (up to 1 Mbps) with SMBus support
  • 2 Single-Edge Nibble Transmission (SENT) Modules for sensor interfacing
  • 4 DMA channels supporting UART, SPI, ADC, IC, OC and Timer data transfers
Special Features
  • 4 Configurable Logic Cell (CLC) Modules with user defined logic gate circuits
  • Programmable Pin Select (PPS) for peripheral pin function mapping
  • On-chip temperature sensor with direct ADC Module connection
Clock and Power Management
  • On-chip 8 MHz Fast RC (FRC) and 32 kHz Low-Power RC (LPRC) oscillators
  • Programmable PLLs with external oscillator clock sources and Reference Clock Output (REFO)
  • Fail-Safe Clock Monitor (FSCM) with 8MHz Back-up Fast RC (BFRC) oscillator
  • Low-Power management modes – Sleep, Idle and Doze
  • Integrated Power-on Reset (POR) and Brown-Out Reset (BOR)
Debugger Development Support
  • In-Circuit and in application programming and debug support (ICSP)
  • On-chip debug trace buffer and run-time watch with 3 complex and 5 simple breakpoints
  • IEEE 1149.2 (JTAG) boundary scan support
Safety Features
  • Dead-Man Timer (DMT) safety feature clocked by instruction fetches
  • Watch Dog Timer (WDT)
  • CodeGuard™ security for program FLASH
  • Programmable Cyclic Redundancy Check (CRC)
  • FLASH ECC Fault Injection testing feature
  • ICSP™ write inhibit
  • Class B Safety Library, IEC 60730
Package Sizes as Small as 4mm x 4mm

Package sizes are available as small as 4mm x 4mm. Both single- and dual-core dsPIC33C devices enable fast deterministic performance for time-critical control applications, providing expanded context selected registers to reduce interrupt latency and bringing faster instruction execution of math-intensive algorithms.

“With 76 dsPIC33C single- and dual-core devices in the family, the common tools, common peripherals and footprint compatibility make it easier for customers to scale as their memory, I/O, performance or budget needs change,” said Joe Thomsen, vice president of Microchip’s MCU16 business unit. “In addition, the dual-core options enable easier software integration for separate software development teams to focus on control algorithms versus communications and housekeeping code.”

All devices in the dsPIC33C family include a fully featured set of functional safety hardware to ease ASIL-B and ASIL-C certifications in safety-critical applications. Functional safety features include multiple redundant clock sources, Fail Safe Clock Monitor (FSCM), IO ports read-back, Flash Error Correction Code (ECC), RAM Built-In Self-Test (BIST), write protection, analog peripheral redundancies and more.

A robust set of CAN-FD peripherals, along with the new support for 150°C operation, make these devices ideally suited for use in extreme operating conditions such as under-the-hood automotive applications.

Development Support

MPLAB® development ecosystem including MPLAB X Integrated Development Environment (IDE), MPLAB Code Configurator, MPLAB XC16 C Compiler toolchain, and MPLAB in-circuit debugger/programmer tools support the dsPIC33C family. Microchip’s motorBench™ Development Suite version 2.0, now supporting high voltage motors up to 600V, is also available to help customers tune motors using the Field Oriented Control (FOC) algorithm.

A variety of development boards and Plug-in Modules (PIMs) are available for the entire family of devices. Development tools for the new devices include the dsPIC33CH Curiosity Board (DM330028-2), the dsPIC33CH512MP508 PIM for general-purpose designs (MA330046), the dsPIC33CH512MP508 PIM for motor control (MA330045), the dsPIC33CK64MP105 PIM for general purpose designs (MA330047), the dsPIC33CK64MP105 PIM for external op amp motor control (MA330050-1) and the dsPIC33CK64MP105 for internal op amp motor control (MA330050-2).

Pricing and Availability

The dsPIC33CH512MP5 devices are available now in 48-pin, 64-pin, and 80-pin TQFP, 64-pin QFN and 48-pin uQFN packages. The dsPIC33CK64MP1 devices are available now in 28-pin SSOP, 28-pin, 36-pin, or 48-pin uQFN and 48-pin TQFP packages. Pricing for the dsPIC33C devices start at $1.34 each in high volume.  The dsPIC33CH Curiosity development board is available now for $39.99 each. The dsPIC33C PIM development boards mentioned above are available now for $25.00 each.

Microchip Technology Inc.
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