New Industry Products

Dialog to License Mixed Signal Embedded Field-Programmable Gate Array Tech

December 12, 2019 by Paul Shepard

Dialog Semiconductor plc and Flex Logix Technologies, Inc. announced a strategic agreement for Dialog to license Flex Logix’s EFLX® Embedded Field-Programmable Gate Array (eFPGA) technology for use in high volume semiconductor Integrated Circuits (ICs), and the EFLX Compiler to program these embedded FPGAs.

Illustrated above, Flex Logix uses a new, patented interconnect, XFLX™, which uses about half the area of the traditional interconnect and uses only 5-7 metal routing layers, but with very high utilization.  Since few metal layers are used, the IP is compatible with almost all metal stacks.

EFLX is a low-power fully functional FPGA that is integrated into SoCs, microcontrollers and other standard or custom ICs, rather than serving as a standalone chip. EFLX cores can be used to upgrade I/O protocols, change encryption algorithms to improve security, enable elements of software-defined radio or accelerate data center algorithms.

Additionally, EFLX can be leveraged by manufacturers or end-users to upgrade both new products and individual systems already installed in the field.

The EFLX arrays are programmed using Verilog or VHDL; and the EFLX Compiler takes the output of a synthesis tool such as Synopsys Synplify and handles packing, placement, routing, timing and bitstream generation. When loaded into the array, the bitstream programs it to implement the desired RTL function.

“Adding eFPGA functionality to our products will give our customers the flexibility to keep pace with rapidly changing market needs,” said Davin Lee, Senior Vice President and General Manager, Advanced Mixed Signal Business Group at Dialog Semiconductor. “By partnering with Flex Logix and leveraging its EFLX eFPGA, there is a massive opportunity to increase the configurability of future Dialog products within several of our target markets, such as IoT, computing, storage and mobile.”

“We are proud to partner with Dialog Semiconductor to deliver additional programmability and flexibility for their customers,” said Geoff Tate, CEO of Flex Logix. “This is just the beginning of a long-term relationship and innovative product roadmap for Dialog and Flex Logix.”

About eFPGA Technology

Flex Logix provides eFPGA cores which have density and performance similar to leading FPGAs in the same process node. EFLX eFPGA is silicon proven in 40nm, 28/22nm, 16/12nm and 14/12nm. 6/7nm EFLX eFPGA is planned for 2020.

Flex Logix’ eFPGA is based on a “tile” called EFLX 4K, which comes in two versions: all logic or mostly logic with some MACs (multiply-accumulators). The programmable logic is called LUTs (look up tables) that can implement any Boolean function. EFLX 4K Logix has 4000 LUT4 equivalents, EFLX 4K DSP has 3000 LUT4s and 40 Multiplier-Accumulators (MACs): the MAC has a 22-bit pre-adder, a 22×22 multiple and a 48-bit post adder/accumulator. MACs can be combined or cascaded to form fast DSP functions.

The magic in FPGAs is the interconnect network that allows any logic block to connect to any other – this is also programmable. Traditional FPGAs use 2D-mesh architectures that require 10+ metal layers and take up much more area than the logic blocks themselves. Typically, in a traditional FPGA the interconnect uses ~80% of the area of the “fabric” (the programmable part of the FPGA consisting of programmable logic and programmable interconnect).

Flex Logix uses a new, patented interconnect, XFLX™ (the subject of the Outstanding Paper award at ISSCC 2014), which uses about half the area of the traditional interconnect and uses only 5-7 metal routing layers, but with very high utilization. Since few metal layers are used, the IP is compatible with almost all metal stacks.

At first glance, XFLX looks like a hierarchical network that has been tried before, but it incorporates numerous improvements to improve spacial locality so as to cut area and reduce metal layers while at the same time maintaining performance.

The EFLX 4K tiles also have an interconnect called ArrayLinx™ which connects tiles into arrays with a mesh interconnect. ArrayLinx allows interconnections between tiles. The XFLX interconnect in each tile connects up to the ArrayLinx. The two types of cores can be mixed in arrays up to 500K LUT4s, with a roadmap to >1M LUT4s.

In FPGA chips, RAM is spread throughout the array. This is possible with EFLX as well: using RAMLinx™ interconnect, RAMs on any kind and size can be integrated between rows or columns of an EFLX array. An example is our TSMC 28HPC+ validation chip is show below.