Arques Technology Offers LDO Power Controller IC

Arques Technology (Austin, TX) announced its new AQ9105, a dual linear regulator designed to meet the voltage specifications for DDR-SDRAM as defined in JEDEC JESD79C, including both the VDDQ memory core voltage and the VTT termination voltage.

With a five-lead TO-263 or TO-252 package, the AQ9105 can generate VDDQ and VTT simultaneously from a single 3.3V input, meeting SSTL DDR specifications. The VDDQ output can source up to 5A, while VTT can source or sink up to ±3A. Using two external resistors to the ADJ/SD pin, the VDDQ voltage can be set between 1.8V to 2.6V. The VTT automatically tracts at half of VDDQ. A shutdown function can be implemented by pulling the ADJ/SD pin to VIN.

With its unique circuit approach, a very low dropout voltage is achieved; VDDQ is typically 600mV at 5A, over the temperature range. Quiescent current is less than 5mA. The AQ9105 provides fast transient response to the dynamic loading of DDR, and has <2% regulation over line, load and temperature variations. It also has built-in over-current limit with foldback and thermal shutdown at 170°C.

The AQ9105 is available now and is priced at $0.45 for 1,000-unit quantities.