Renesas Electronics Corporation introduced four new RX651 32-bit microcontrollers supplied in ultra-small 64-pin BGA and LQFP packages. The new lineup expands the company’s RX651 MCU Group with a 64-pin (4.5mm x 4.5mm) BGA package that reduces the footprint size by 59% compared to the 100-pin LGA, and a 64-pin (10mm x 10mm) LQFP that provides a 49% reduction versus the 100-pin LQFP.
The MCUs meet advanced security needs for endpoint devices that employ compact communication and sensor modules in building automation, industrial, network control, and smart metering systems operating at the IoT edge.
“The explosive growth of the IoT and Industry 4.0 has sparked the need for higher performance, smaller form factor connectivity modules that support the various security aspects required with IoT connectivity—such as confidentiality, data integrity, and availability. The RX651 delivers on this need with smaller MCU package sizes that are ideal for compact IoT applications, without compromising performance,” said Daryl Khoo, Vice President of Marketing, IoT Platform Business Division, Renesas Electronics Corporation. “The 64-pin RX651 MCUs give customers the small footprint, high performance, and security features they need to safeguard their connected industrial and manufacturing systems against cyber-attacks.”
Renesas notes that the increase in endpoint devices operating at the edge has increased the need for secure over-the-air (OTA) firmware updates. The new RX651 devices support this reprogramming demand with integrated TSIP, enhanced flash protection, and other technology advancements that the company says offer a more secure and stable solution than other available solutions on the market.
Enables advanced IoT edge devices
The compact 64-pin MCUs with enhanced security features are based on the company’s high-performance RXv2 core and its 40nm process that provides excellent performance with a 520 CoreMark® score at 120 MHz, and strong power efficiency with a 35 CoreMark/mA score according to EEMBC® Benchmarks.
Easy in-the-field firmware updates
The integrated dual-bank flash memory facilitates high root-of-trust levels through a combination of code flash area protection to protect boot code from reprogramming; TSIP that protects the encryption key; encryption hardware accelerators including AES, 3DES, RSA, SHA, and TRNG.
The dual bank flash function supports both background operation (BGO) and SWAP, making it easier for manufacturers to perform in-the-field firmware updates securely and reliably.
Designed for connected industrial environments, the RX651 MCUs monitor the operating state of machinery from both inside and outside the factory. This monitoring enables data exchanges to change production instructions, and reprogram MCU memory to update equipment settings.
Summary of Features of RX65N and RX651 Group
- 32-bit RXv2 CPU core
- operating frequency: 120MHz Capable of 240 DMIPS in operation at 120MHz
- Single precision 32-bit IEEE-754 floating-point
- Two types of multiply-and-accumulation unit (between memories and between registers)
- 32-bit multiplier (fastest instruction execution takes one CPU clock cycle)
- Divider (fastest instruction execution takes two CPU clock cycles)
- Fast interrupt
- CISC Harvard architecture with 5-stage pipeline
- Variable-length instructions: Ultra-compact code
- Supports the memory protection unit (MPU)
- JTAG and FINE (one-line) debugging interfaces
- Low-power design and architecture
- Operation from a single 2.7V to 3.6V supply
- Low power consumption:
- A product that supports all peripheral functions draws only 0.19mA/MHz (Typ.).
- RTC is capable of operation from a dedicated power supply.
- Four low-power modes
- On-chip code flash memory
- Supports versions with up to 2Mbytes of ROM
- No wait cycles at up to 50MHz or when the ROM cache is hit, onewait state at up to 100MHz, two-wait state at above 100MHz
- User code is programmable by on-board or off-board programming.
- Programming/erasing as background operations (BGOs)
- A dual-bank structure allows exchanging the start-up bank.
- On-chip data flash memory
- 32Kbytes, reprogrammable up to 100,000 times
- Programming/erasing as background operations (BGOs)
- On-chip SRAM, no wait states
- 256Kbytes/640Kbytes of SRAM (no wait states)
- 8Kbytes of standby RAM (backup on deep software standby)
- Data transfer
- DMACAa: 8 channels
- DTCb: 1 channel
- EXDMAC: 2 channels
- DMAC for the Ethernet controller: 1 channel
- Reset and supply management
- Power-on reset (POR)
- Low voltage detection (LVD) with voltage settings
- Clock functions
- External crystal resonator or internal PLL for operation at 8MHz to 24MHz
- Internal 240kHz LOCO and HOCO selectable from 16MHz, 18MHz, and 20MHz
- 120kHz clock for the IWDTa
- Real-time clock
- Adjustment functions (30 seconds, leap year, and error)
- Real-time clock counting and binary counting modes are selectable
- Time capture function (for capturing times in response to event-signal input)
- Independent watchdog timer
- 120kHz (1/2 LOCO frequency) clock operation
- Useful functions for IEC60730 compliance
- Oscillation-stoppage detection, frequency measurement, CRCA, IWDTa, self-diagnostic function for the ac-dc converter, etc.
- Register write protection function can protect values in important registers against overwriting.
- Various communications interfaces
- Ethernet MAC (1 channel)
- PHY layer (1 channel) for host/function or OTG controller (1 channel) with full-speed USB 2.0 transfer
- CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up to 2 channels)
- SCIg and SCIh with multiple functionalities (up to 11 channels) Choose from among asynchronous mode, clock-synchronous mode, smart-card interface mode, simplified SPI, simplified I2C, and extended serial mode.
- SCIi with 16-byte transmission and reception FIFOs (up to 2 channels)
- I2C bus interface for transfer at up to 1Mbps (up to 3 channels)
- Four-wire QSPI (1 channel) in addition to RSPIc (3 channels)
- Parallel data capture unit (PDC) for the CMOS camera interface
- Graphic-LCD controller (GLCDC)
- 2D drawing engine (DRW2D)
- SD host interface (optional: 1 channel) with a 1-bit or 4-bit SD bus for use with SD memory or SDIO
- SD slave interface (optional: 1 channel) with a 1-bit or 4-bit SD bus for use with SD host interface
- MMCIF with 1-bit, 4-bit, or 8-bit transfer bus width
- External address space
- Buses for full-speed data transfer (max. operating frequency of 60MHz)
- 8 CS areas
- 8-bit, 16-bit, or 32-bit bus space is selectable per area
- Independent SDRAM area (128Mbytes)
- Up to 25 extended-function timers
- 16-bit TPUa, MTU3a
- 8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2 channels)
- 12-bit ac-dc converter
- Two 12-bit units (8 channels for unit 0; 21 channels for unit 1)
- Self-diagnosis, detection of analog input disconnection
- 12-bit dc-ac converter: 2 channels
- Temperature sensor for measuring temperature within the chip
- Encryption functions (optional)
- AES (key lengths: 128bits, 192bits, and 256bits)
- Trusted Secure IP (TSIP)
- Up to 136 pins for general I/O ports (RX65N, not the newly released RX651)
- 5V tolerance, open drain, input pull-up, switchable driving ability
- Operating temp. range
- D-version: -40°C to +85°C
- G-version: -40°C to +105°C
Pricing and Availability
The RX651 64-pin MCUs are now available from Renesas Electronics’ worldwide distributors with prices starting at $4.58 in 10,000-unit quantities.
Also now available to verify performance and jumpstart system development are the company’s low-cost target boards and starter kits, combined with the e² studio integrated development environment.