Cadence Design Systems, Inc. announced that Yamaha Corporation utilized components of the Cadence® Low-Power Solution to achieve a 50 percent reduction in leakage power in its newest chip for smartphones. The Cadence tools used by Yamaha consisted of Cadence Encounter® RTL Compiler (RC), Cadence Encounter Conformal® Low Power (CLP) and Cadence Encounter Digital Implementation (EDI) System.
"Low power is critical for our new mobile chip designs," said Shuhei Ito, development director, Yamaha Corporation. "Because the tools in the Cadence Low-Power Solution support the Common Power Format, it allowed us to leverage advanced power management techniques, which resulted in better power and performance and shorter turnaround time for our design."
The Cadence Low-Power Solution supports many advanced low-power techniques such as multi-supply voltage, power shutoff and multi-bit cell inferencing, which are critical to reducing power. In addition to reducing leakage power, Yamaha utilized the solution to achieve design closure at the target performance and power levels. The design tools in the solution support a consistent power management intent as described in the Common Power Format (CPF) for all design phases such as implementation and verification from register-transfer level (RTL) to GDSII.