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Design Features
Shaping Efficiency Using Digital Algorithms
David Williams
Director of Systems Engineering
CHiL Semiconductor Corporation
The onslaught of efficiency requirements for multiphase dc-dc voltage regulators (VRs) has caused a major shift in VR solutions throughout the computing industry. While such computing industry specifications as Climate Savers or Energy Star® do not specify exact dc-dc efficiency requirements, they make it abundantly clear that efficiency from 20 to 100% load needs to constantly improve. Major OEM customers, especially in the server industry, are demanding even higher efficiency levels than industry forums are proposing. To shape the efficiency across the CPU’s entire load, as well as the memory, CHiL Semiconductor Corporation has implemented several digital algorithms in its digital power management IC families. CHiL’s digital algorithms combine to create a shaped efficiency curve, which results in high efficiency across the entire load line.
Efficiency Evolution and Shaping
The efficiency of VR solutions, whether for CPU or memory on servers, or for graphics controllers on graphics boards or in high performance computing (HPC) applications, has evolved over time as a function of cost and size. Key factors driving the need for higher efficiency include total cost of ownership (TCO) and the concern for greener solutions. Figure 1, showing multiphase systems converting 12 to 1.2V, highlights the evolution of efficiency in servers from initial levels in 2008 to shaped efficiencies available in 2010.
Figure 1. Evolution of VR Efficiency in Server Systems
Initially, efficiency and TCO were not a concern, and efficiency typically peaked near the 88 percent range. At lower currents, in idle states, the efficiency dropped off due to the switching losses of multiple phases. The introduction of the power savings indicator (PSI) in 2008 allowed VR solutions to turn off all but one phase at lower load currents, raising the efficiency in idle states. The efficiency over various operating modes, especially in servers where 20-100% operation is the most important, was still quite low.
Solutions that strived to achieve higher efficiency would use discrete MOSFETs (metal-oxide-semiconductor field-effect transistors) with lower RDS(on) (defined as the resistance when the device is in saturation) in the solution, driving the higher load efficiency to higher points, costing efficiency at lower loads due to increased drive losses. Integrated solutions, whether monolithic or multi-chip, reduced parasitic losses and increased efficiencies at the low range.
The shaped efficiency curve created by the combination of CHiL’s digital algorithms results in high efficiency across the entire load line. The high efficiency is accomplished using two primary methodologies: Dynamic Phase Control and Variable Gate Drive.
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