Power Components

SiC Devices, Power in 3D Packaging, and More at IEDM 2017

New discoveries about SiC mobility, Extreme 3D integration and Thermal effects in 3D monolithic ICs are among the topics that will be explored in depth at the 63rd  International Electron Devices Meeting (IEEE IEDM 2017) to be hosted 2-6 December, 2017 at the Hilton San Francisco Union Square

New Discoveries About SiC Mobility: Transistors made from silicon carbide (SiC) can operate at higher temperatures and/or voltages than silicon devices, making them a good fit for power-management applications. However, a better understanding of SiC’s carrier-transport properties is needed for more efficient, better-performing SiC devices.

A semiconductor’s carrier-transport properties determine its “mobility,” or how fast electrons and holes can move through it. Carrier mobility-limiting factors in SiC include Coulomb scattering, surface-roughness-scattering, and limitations imposed by phonons (vibrations in the material).

SiC carrier-transport studies to date have relied on computer models and simulations, and while they have shown that the dominant mobility-limiting factors are Coulomb scattering at low voltages and surface roughness at higher voltages, the intrinsic magnitude of the phonon-limiting effect has been unclear.

Different values for it have been assumed for modeling studies. At the IEDM, a team led by Mitsubishi will tell how they were able to observe phonon-limited mobility in SiC experimentally for the first time.

They found it is, at most, one-fourth of presumed values. They also found that surface roughness isn’t the dominant mobility-limiting factor at high voltages. (Paper 9.3, “Determination of Intrinsic Phonon-Limited Mobility and Carrier Transport Property Extraction of 4H-SiC MOSFETs,” M. Noguchi et al, Mitsubishi/Univ. Tokyo)

Extreme 3D Integration: In a paper in the 3D Integration and Packaging Focus Session, an IBM-led research team will describe several novel heat removal and power delivery technologies aimed at making so-called computing cubes a reality. Computing cubes comprise packaged stacks of chips that can have memory-on-logic or logic-on-logic functionality.

The researchers will describe four enabling technologies that were integrated to build computing cubes of various sizes and levels of performance: Dual-side cooling of a stack of chips – The researchers formed embedded microcavities in a silicon interposer layer on one side of the stack, and coupled it with a backside cold plate through which liquid coolant flows.

Interlayer cooling – They formed microcavities in the backside of each die in the stack, through which coolant flows; Integrated voltage regulators – They built distributed power ICs for granular voltage scaling throughout the cube for energy-efficient operation. The CMOS components of the power ICs are integrated with the cube’s logic circuitry, while their passive components are in the interposer layer.

Electrochemical power delivery – They added soluble redox-active compounds to the cooling fluid to enable it to deliver power throughout the cube electrochemically. (Paper 3.7, “Towards Cube-Sized Compute Nodes: Advanced Packaging Concepts Enabling Extreme 3D Integration,” T. Brunschwiler et al, IBM/ETH/FhG/Murata/Tyndall National Institute)

Thermal Effects in Monolithic 3D ICs: Stacking and interconnecting a number of chips is one way to build a 3D integrated circuit, but another way is to build a 3D IC monolithically. Monolithic 3D ICs are fabricated step-by-step with sequential placement and connection of devices located in different layers of the same chip.

One issue with the monolithic approach is heat dissipation, because heat can negatively affect transistor electrical characteristics, performance and reliability. A particular area of concern is the need to understand the thermal effect of the second layer on the performance of devices in the first layer. A research team led by CEA-Leti investigated this in 3D ICs made from SOI wafers with 7nm-thick Si layers and a base oxide thickness of 145nm.

They used multiple p- and n-channel MOSFET configurations, heater-sensor arrangements and thermometry techniques. They found that the self-heating of individual transistors is more significant than thermal coupling between the layers.

Moreover, for the first time they experimentally validated that the increase in a device’s channel temperature – as measured by gate-resistance thermometry – matches the value mathematically derived from the subthreshold slope.

That is an important advance for monolithic 3D IC technology, because it can be used to anticipate and manage thermal effects in both logic and analog applications. (Paper 7.6, “Thermal Effects in 3D Sequential Technology,” K. Triantopoulos et al, CEA-Leti/Univ. Grenoble Alpes/IMEP-LAHC)

2017 International Electron Devices Meeting
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