Sonics, Inc. upgraded its ICE-P3™ Energy Processing Unit (EPU), the flagship member of the ICE-Grain™ Family of EPU products, to add a new programmable Sequencer. The Sequencer enables designers of power-sensitive chips like systems-on-chip (SoC) and microcontrollers (MCU) to significantly improve control over both on-chip and external voltage and frequency resources to minimize energy consumption.
The Sequencer combines the flexibility of resource control offered by software-based solutions with the minimized latency, area, and power provided by hardware-based solutions.
“With this new Sequencer in ICE-P3, SoC and MCU designers now have the capability to implement event-driven resource control without the power and interrupt latency overhead associated with using a CPU running power management software,” said Drew Wingard, CTO of Sonics. “With its simplified instruction set and efficient implementation, our Sequencer empowers designers to configure ICE-P3’s operating point controllers to directly manage voltage and frequency sources to minimize chip energy consumption.”
The Sequencer has a very small physical footprint and flexibly supports a wide range of approaches for controlling frequency and/or voltage resources, both on-chip and off-chip. Key to the Sequencer’s speed, area efficiency, and ease of use is its index table, which associates a starting address and dedicated storage for each desired resource state.
When the operating point controller requests a new state by changing the performance index, the Sequencer executes instructions that compose and generate communication transactions to the resource and wait for handshake responses or timer values.
Compatible resource states may share the same starting address, using the per-index storage to distinguish the requested resource values. The initial Sequencer release focuses on two styles of resource communication: control via ARM® AMBA® write transactions and/or general purpose input/output (GPIO) signaling. In the future, Sonics plans to expand the supported protocols and add additional Sequencer commands that provide richer interaction with the controlled resources or other system components.
Sequencer Implements DVFS, Abstracts PMIC Selection, and Replaces Custom Logic for Host CPU Boot Cycle
As with many features of ICE-P3, the Sequencer is highly configurable to give the designer complete control over flexibility versus implementation cost. For example, consider a dynamic voltage and frequency scaling (DVFS) implementation where ICE-P3 manages both an on-chip clock generation unit (CGU) with an interface known at design time and a voltage regulator on an external power management integrated circuit (PMIC) supplied by the end customer.
By configuring a CGU Sequencer with read-only instructions, minimal general purpose register (GPR), no AMBA interface, and only enough index table data storage to hold the unique, per-state CGU control values, the designer minimizes Sequencer area while still providing programmable frequency values.
In contrast, the designer may abstract the choice of PMIC by configuring the voltage Sequencer with programmable instruction memory, a few GPRs for storing resource addresses and composing transactions, and programmable index table starting addresses. This voltage Sequencer could then be programmed at runtime to choose between I2C and I3C external interfaces, in addition to the wide variety of register programming models associated with PMICs from different vendors.
The host CPU power up and boot cycle is another application in which the Sequencer reduces design risk and provides power savings. In the conventional approach to CPU power up common with many platforms, the designer must build custom logic that sequences the clocks and enables power to the CPU, then releases its reset pin so it can boot, i.e. initialize all the interfaces, set up the interrupt controllers and timers, and load the operating system.
This custom logic tends to be very chip-specific and the chip simply won’t work if the logic fails, so the approach carries significant risk.
Using an EPU to handle CPU power up and boot makes this approach just another facet of power control. Rather than having different schemes for processor boot versus power control after boot, this becomes just another set of states.
The designer can use one or more Sequencers to implement the initial resource sequencing and reset control required to boot the host processor. By correctly configuring the power on states for the EPU, the Sequencers replace the conventional custom logic and remove its potential risk.
The Sequencer is available now in Sonics’ ICE-P3 EPU.